1. Field of the Invention
This invention relates to a method and an apparatus for formatting and coding a digital video signal of each frequency band after dividing the same into a plurality of frequency bands.
2. Description of Related Art
Conventionally, a digital video signal has been coded in such a manner as disclosed in Japanese Patent Laid-Open No. 1-253382 (1989) and U.S. Pat. No. 4,394,774. The conventional coding method will be discussed hereinbelow with reference to these prior arts.
Referring to FIG. 1, there is shown a block diagram of the structure of a conventional digital video signal coding apparatus disclosed in Japanese Patent Laid-Open No. 1-253382 referred to above. A principal movement estimating circuit 101 regulates a principal displacement vector whose image-to image difference is minimum by each preceding image and outputs the vector to a scan converting circuit 102 and coding circuit 105. The scan converting circuit 102 forms a two-dimensional block of 8 picture elements.times.8 lines, thereby forming a three-dimensional block with the four two-dimensional blocks of four consecutive images. Every four two-dimensional blocks in each three-dimensional block are shifted in space from one image to another by the displacement vector outputted from the circuit 101. The three-dimensional block outputted from the scan converting circuit 102 is processed by an orthogonal transform at a three-dimensional orthogonal transforming circuit 103. An inverse quantizing and normalizing circuit 104 normalize and quantize coefficients outputted from the three-dimensional orthogonal transforming circuit 103. The normalization weights coefficients by multiplying or dividing them according to a parameter related to the filling rate of a rate control memory 106 and the coefficients themselves. The quantization converts the normalized value of each coefficient expressed at a floating point to an integer.
An output of the quantizing and normalizing circuit 104 is outputted to the coding circuit 105 which transmits a word of Huffman code among words stored in a memory and regulated beforehand, and another word indicating an address of the coded value to the rate control memory 106 by each non-zero quantized value. The address simultaneously with the one-dimensional scan in the three-dimensional block are regulated by coding the length of a sequence of zeros. The coding circuit 105 provided with a variable length coding function is a generally common model. The rate control memory 106 ensures the outputting rate to be constant. The above-mentioned U.S. Pat. No. 4,394,774 reveals the method to reduce the coding rate of the sequence of zeros outputted from the rate control memory 106.
In FIG. 2, a coding circuit 105 of a different embodiment is shown. The coding apparatus 105 can be arranged in such structure as shown in FIG. 2 wherein each of the apparatuses is provided with m paths in parallel to receive all the values to be coded. More specifically, these values are inputted to respective storing circuits along the paths, and each storing circuit has two memories functioning as a flip-flop. The value of a given three-dimensional block is written in one of the two memories, while the value of the preceding block is read by the other memory in the order corresponding to a new scan. FIGS. 3(a) and 3(b) indicate two types of scanning for reading, i.e., FIG. 3(a) is a type allowing minimization of the rate of a block having a fixed content and FIG. 3(b) is a type related to a moving picture. Each output from the storing circuits 111a-111m is outputted to respective associating circuits 112a-112m which are coding circuits performing variable length coding according to the U.S. Pat. No. 4,394,774. Each output from the circuits 112a-112m is inputted to a counting and judging circuit 113. The circuit 113 counts the number of bits used to code each three-dimensional block for scanning, thereby to determine a scan which minimizes the rate of the three-dimensional block. Moreover, the circuit 113 controls an output of a branching circuit 114 storing bits outputted from each coding circuit, and ensures the transfer of bits corresponding to the optimum coding of the three-dimensional block to a multiplexing circuit 115. The multiplexing circuit 115 multiplies the bits based on a selected scanning index and transfers the bits to a decoding apparatus for reconstruction of the block, and assures the transfer of a principal displacement vector determining the images when each of four groups of images is started.
According to a conventional coding method of a digital video signal, when the coefficients, after being processed by the three-dimensional orthogonal transform, are scanned in the one dimension, the coding amount is reduced by selecting the scanning type of FIG. 3(a) for a static part and the scanning type of FIG. 3(b) for a moving part. In combination of the sub-dividing and three-dimensional orthogonal transform, namely, when the three-dimensional orthogonal transform is applied to each band component after the digital video signal is divided into a plurality of frequency band, however, the scanning types shown in FIGS. 3(a) and 3(b) are not considered optimum particularly for components including high frequencies.
The quantization level of the coefficients outputted from the three-dimensional orthogonal transforming circuit 103 is decided by a parameter related to the filling rate of the rate control memory 106 and the coefficients themselves. In this case, if both a flat part and an edge part exist within one block, noises on the flat part of a reproduced image are very conspicuous.
In the Japanese Patent Laid-Open No. 1-253382, if a utilizable signal is treated according to the interlaced scanning, the signal is converted to a video signal in the sequential scanning from prior to the coding. Therefore, as indicated in FIG. 4, one image is constituted by every frame, and a horizontal direction 1 is set as a first dimensional direction, a vertical direction 2 as a second dimensional direction and a time direction 3 as a third dimensional direction thereby to construct a three-dimensional block, and the redundancy of the video signal is eliminated by performing orthogonal transform on the three-dimensional block.
Meanwhile, the interlaced scanning method is employed in the actual television screen as shown in FIG. 5. This method can prevent flickering without increasing the amount of information to be transmitted when transmitting the moving image information. Accordingly, one screen is completely scanned by half the number of scanning lines shown in FIG. 5. Lines not scanned on the preceding screen are scanned on the succeeding screen, so that the vertical resolution of the image is restricted from being worsened. Since the number of screens transmitted within the same period is increased twice according to the interlaced scanning as compared with the sequential scanning, the occurrence of the flickering is restricted. The screen roughly scanned as above is called a field. One frame is formed of the two successive fields as illustrated in FIG. 6, and therefore the scanning speed is approximately 60 fields per second according to the NTSC (National Television System Committee) method.
In the conventional digital video signal coding method, a three-dimensional block is constituted by a video signal in the sequential scanning form, which is the reason why the redundancy of the video signal in the interlaced scanning form cannot be effectively eliminated. Particularly, if the video signal in the interlaced scanning form with large motion is coded in the same manner as the video signal in the sequential scanning form, a two-dimensional block is formed with the spatial displacement and time displacement mixed, making it difficult to eliminate the redundancy of the video signal.
FIG. 7 is a block diagram showing the structure of a conventional coding apparatus disclosed, for example, in IEEE Transactions on Consumer Electronics, Vol. 34, No. 3 (August 1988) under the title of "AN EXPERIMENTS DIGITAL VCR WITH 40 MM DRUM, SINGLE ACTUATOR AND DCT-BASED BIT-RATE REDUCTION". Referring to this FIG. 7, a block formatting circuit 121 divides an inputted digital video signal into a plurality of blocks and outputs the video signal of each block to a DCT circuit 122. The DCT circuit 122 processes each block outputted from the block formatting circuit 121 by DCT (Discrete Cosine Transform), and outputs the obtained coefficients to a weighting circuit 123. Each coefficient from the DCT circuit 122 is weighted at the weighting circuit 123 and then outputted to an adaptive quantizing circuit 124. The adaptive quantizing circuit 124 holding a plurality of quantization tables of different quantizing step widths quantizes the weighted coefficient according to the optimum quantizing step width and outputs it to a variable length coding circuit 125. The variable length coding apparatus 125 performs variable length coding on the quantized coefficient and outputs the variable length coded data to a buffer memory 126. The buffer memory 126 converts the data to a fixed rate and stores the same. The variable length coded data is outputted with a fixed output rate. A buffer controller 127 switches the quantizing step width at the adaptive quantizing circuit 124 so that the buffer memory 126 does not overflow, and at the same time it selects the coefficient to be coded at the variable length coding circuit 125.
The operation of the above-described apparatus will now be discussed more in detail. An inputted digital video signal is composed of, e.g., a luminance signal and two color difference signals. These signals are time-divided at the formatting circuit 121 and divided into blocks, for example, 8 picture elements.times.lines and outputted to the DCT circuit 122. The video signal in each block is processed by DCT on 8 picture elements in the horizontal and in the vertical directions at the DCT circuit 122. Supposing that the video signal is expressed by x(i,j) (i,j=0, 1, . . . , 7), DCT on 8 picture elements in the horizontal direction is conducted in a manner as follows: ##EQU1## Then, DCT on 8 picture elements in the vertical direction is performed on the transformed video signals f(0,j), f(m,j) in accordance with equations below: ##EQU2## Accordingly, the video signal is expressed as a coefficient F(m,n) (m,n=0, 1, . . . , 7) and outputted to the weighting circuit 123.
Each coefficient inputted to the weighting circuit 123 is processed by weighting. Concretely, since the human eye is weak to a high spatial frequency, weighting with small rate is performed on a zone including high spatial frequency components, whereas weighting with large rate is performed on a zone including low spatial frequency components. A weighting function W(m,n) is represented by the following equation; ##EQU3##
The output from the weighting circuit 123 is quantized at the adaptive quantizing circuit 124. Based on the coefficient in each block and the quantizing parameter outputted from the buffer controller 127, the adaptive quantizing step width is selected at the adaptive quantizing circuit 124. The weighted coefficient is quantized in accordance with the selected optimum quantizing step width. Concretely, a coarse quantizing step width is selected for the video data with a leading end of strong contrast, or a fine quantizing step width is selected for the video data of a detailed part of small amplitude.
The quantized coefficient is variable length coded at the variable length coding circuit 125 and stored in the buffer memory 126. The amount of data stored in the buffer memory 126 is checked by the buffer controller 127 so as to prevent the buffer memory 126 from overflowing. The buffer controller 127 decides the quantizing parameter in accordance with the amount of data stored in the buffer memory 126. The quantizing step width in the adaptive quantizing circuit 124 is changed in accordance with this quantizing parameter, and also the coefficient to be coded in the variable length coding circuit 125 is selected in accordance with the amount of data in the buffer memory 126. In other words, the buffer controller 127 increases the reduction rate of data when the buffer memory 126 stores a lot of data. On the other hand, the buffer controller 127 reduces the reduction rate when the amount of data stored in the buffer memory 126 is small. Owing to the adjustment as above at the buffer controller 127, the buffer memory 126 is prevented from overflowing. The data stored in the buffer memory 126 is read with a fixed output rate.
In the conventional coding apparatus described above, when a digital video signal is divided into sub-bands and orthogonal transform is performed on the blocks in each sub-band, since the frequency response of each sub-band is different by the influences of the folding of the sub-sampling, weighting to be fitted for each sub-band is necessary.
As disclosed in Japanese Patent Laid-Open No. 63-38385 (38385/1988), a sampled video signal can be periodically downsampled in order to reduce the coding rate of the signal. FIGS. 9 and 10 are block diagrams showing the structure of a transmission side (recording side) and a receiver side (reproducing side) of a coding apparatus, respectively, wherein the sub-sampling method referred to above is employed for a color video signal.
Referring first to FIG. 9, the transmission side will be explained. A color video signal, for example, in NTSC system is inputted to an input terminal 131. When this color video signal is outputted to an A/D converter 132, a digital color video signal quantized in 8 bits per one sample with a sampling frequency of, e.g., 4 fsc (fsc: color sub carrier frequency) is obtained. The obtained digital color video signal is outputted to a sub-sampling circuit 133 and then to a formatting circuit 134. A prefilter for band restriction is not provided in the former stage of the sub-sampling circuit 133, therefore high frequency components of the color video signal are not lost.
In the sub-sampling circuit 133, the digital color video signal is sampled with a sampling frequency 2 fsc. At the formatting circuit 134, the digital color video signal is further converted to a continuous signal per every two-dimensional block which is a coding unit. According to the example shown in FIG. 9, one block obtained by dividing the screen of one field is composed of 8 picture elements.times.4 lines, i.e., 32 picture elements. FIG. 11 illustrates one block, in which a solid line indicates a line of a field of an odd number and a broken line shows a line of a field of an even number. One block can be a three-dimensional block constituted by four two-dimensional areas in each of four frames. The picture elements in the block are downsampled as shown in FIG. 12 at the sub-sampling circuit 133 provided prior to the formatting circuit 134. In consequence, the number of picture elements in each block is 16. A symbol o in FIG. 12 is a sub-sampled picture element, a symbol x being a downsampled picture element.
The output of the formatting circuit 134 is inputted to a dynamic range (DR) detecting circuit 135 and to a delay circuit 136. The DR detecting circuit 135 detects the dynamic range and minimum value MIN by every block. The picture element data PD from the delay circuit 136 is outputted to a subtractor 137, where the picture element data PDI from which the minimum value MIN is removed is formed.
Into a quantizing circuit 138 are inputted the picture element data PDI without the minimum value and the dynamic range DR. The picture element data PDI is quantized at the quantizing circuit 138 in compliance with the dynamic range DR. The quantizing circuit 138 outputs a code signal DT with one picture element data converted to 4 bits.
The code signal DT from the quantizing circuit 138 is outputted to a framing circuit 139. The dynamic range DR (8 bits) and minimum value MIN (8 bits) are inputted as an additional code of each block to the framing circuit 139. The framing circuit 139 executes error correction coding on the code signal DT and additional code, and also adds a synchronizing signal. The transmission data obtained at an output terminal 140 of the framing circuit 139 is outputted to a transmission line such as a digital line, etc. In the case of a digital VTR, the output signal is sent to a rotary head through a recording amplifier and a rotary transformer and the like.
The receiver side will be depicted with reference to FIG. 10. The received data is inputted to a de-framing circuit 142 through an input terminal 141. The code signal DT and additional code DR, MIN are separated and processed by error correction at the de-framing circuit 142. The code signal DT and dynamic range DR are outputted, to a decoding circuit 143.
The decoding circuit 143 carries out the treatment reverse to that of the quantizing circuit 138 at the transmission side. That is, the data, with the minimum level removed, is decoded to a representative level, which data is added with the 8-bit minimum value MIN at an adder 144, thereby decoding the original picture element data. The output of the adder 144 is inputted to a de-formatting circuit 145 which, in the process reverse to that of the formatting circuit 134, converts the decoded data in the order of blocks to those in the same order as scanning. When the output of the de-formatting circuit 145 is inputted to an interpolating circuit 146, the data of the thinned picture elements is interpolated by the sub-sampling data therearound. The digital color video signal with the sampling frequency 4 fsc from the interpolating circuit 146 is outputted to a D/A converter 147. Accordingly, an analog color video signal is obtained at an output terminal 148 of the D/A converter 147. In the case where a prefilter is not provided at the transmission side, there is a possibility that a folding distortion is generated, for example, at a point where the luminance level is suddenly changed, and therefore a circuit to remove the distortion can connected to an output side of the interpolating circuit 146.
Although the coding rate is reduced in the conventional coding apparatus of the above-discussed structure, there still are involved some problems that the resolution of a moving picture is lowered, an occurrence of the folding distortion increases the quality deterioration etc. The conventional coding apparatus is not sufficient for coding to obtain an image of good quality.
FIGS. 13 and 14 are block diagrams showing the structure of a conventional sub-band dividing/synthesizing circuit disclosed, e.g., IEEE Transactions on Circuits and System, Vol. 35, No. 2 (February 1988) "Sub-Band Coding of Monochrome and Color Images".
In FIG. 13, a digital video signal inputted through an input terminal 151 is outputted to a horizontal low pass filter. 152 (referred to as a horizontal LPF 152 hereinafter) for restricting a horizontal frequency of the video signal. The horizontal LPF 152 is a filter with even number taps, having a frequency response shown in FIG. 15. When the function of the horizontal LPF 152 is designated by h1(n) (h =0, 1, . . . , N-1; N being an even number), the following equation is held; EQU h1(n)=h1(N-n-1), n=0, . . . , (N/2)-1
In other words, if the input video signal is 256 picture elements.times.256 lines, the horizontal LPF 152 outputs a signal expressed by a formula (1) below by each line x(n) (n =1, . . . , 256) of the video signal; ##EQU4##
On the other hand, the inputted digital video signal is inputted also to a horizontal high pass filter 153 (referred to as a horizontal HPF 153 hereinafter) for restricting a horizontal frequency of the video signal. The horizontal HPF 153 is a filter with even number taps, having a frequency response b of FIG. 15. The function h2(n) (n=0, EQU h2(n)=h1(n).multidot.(-1).sup.n
Therefore, EQU h2(n)=-h2(N-n-1), n=0, . . . , (N/2)-1
In other words, the horizontal HPF 153 outputs a signal represented by a formula (2) below by each line x(n) (n=1, ##EQU5##
The outputs of the horizontal LPF 152 and horizontal HPF 153 are inputted to horizontal 2:1 sub-sampling circuits 154a, 154b respectively, to reduce the picture elements in the horizontal direction to half. The outputs of the horizontal 2:1 sub-sampling circuits 154a, 154b are inputted to vertical low pass filters 155a, 155b (referred to as vertical LPFs 155a, 155b) for restricting a vertical frequency respectively. The vertical LPFs 155a, 155b are filters with even number taps having the frequency response a in FIG. 15. The function h3(m) (m=0, . . . , M-1: M being an even number) satisfies EQU h3(m)=h3(M-m-1), m=0, , (M/2)-1
That is to say, the vertical LPFs 155a, 155b output a signal represented by the following formula by each line w(m) (m=1, . . . , 256) of the video signal outputted from the horizontal 2:1 sub-sampling circuits 154a, 154b respectively; ##EQU6##
The outputs of the vertical LPFs 155a, 155b are respectively inputted to vertical 2:1 sub-sampling circuits 157a, 157c, where the number of picture elements in the vertical direction is reduced to half. The outputs of the vertical 2:1 sub-sampling circuits 157a, 157c are outputted from respective output terminals 158a, 158c. The signal outputted from the output terminal 158a is a signal of the LL frequency band of FIG. 16. Moreover, the signal outputted from the output terminal 158c is a signal in the HL frequency band of FIG. 16. Meanwhile, the outputs of the horizontal 2:1 sub-sampling circuits 154a, 154b are also inputted to vertical high pass filters 156a, 156b (referred to as vertical HPFs 156a, 156b hereinafter) for restricting a vertical frequency. The vertical HPFs 156a, 156b are filters with even number taps, having the frequency response b shown in FIG. 15, the function h4(m) (m=0, . . . , M-1) being EQU h4(m)=h3(m) (-1).sup.m
Therefore, EQU h4(m)=-h4(M-m-1), m=0, . . . , (M/2)-1
In other words, the vertical HPFs 156a, 156b output a signal expressed as follows by each line w(m) (m=1, . . . , 256) of the video signal outputted from the respective horizontal 2:1 sub-sampling circuits 154a, 154b; ##EQU7##
The outputs of the vertical HPFs 156a, 156b are inputted to vertical 2:1 sub-sampling circuits 157b, 157d respectively. After the number of picture elements in the vertical direction is reduced to half at the circuits 157b, 157d, the signal is outputted from each output terminal 158b, 158d. The signal outputted from the output terminal 158b is a signal of the LH frequency band in FIG. 16, and that outputted from the output terminal 158d is a signal in the HH frequency band of FIG. 16.
The sub-band dividing circuit operates in the manner as described hereinabove. The four sub-divided signals are coded by predictive coding, orthogonal transform, etc. and outputted. At the decoding side, these signals are combined after being decoded. A sub-band synthesizing circuit shown in FIG. 14 operates in reverse of the sub-band dividing circuit of FIG. 13. Specifically, the outputs from the output terminals 158a-158d are inputted to the corresponding input terminals 159a-159d, interpolated with 0 at vertical 1:2 interpolating circuits 160a-160d respectively. As a result, the number of picture elements in the vertical direction is increased twice. The outputs from the vertical 1:2 interpolating circuits 160a, 160c are inputted to vertical LPFs 161a, 161b respectively. The vertical LPFs 161a, 161b are filters having the completely same frequency response as the vertical LPFs 155a, 155b, and output a signal described below by each line u1'(m) (m=1, . . . , 256) of the output video signal outputted from the vertical 1:2 interpolating circuits 160a, 160c respectively; ##EQU8##
In the meantime, the outputs of the vertical 1:2 interpolating circuits 160b, 160d are respectively inputted to vertical HPFs 162a, 162b. The vertical HPFs 162a, 162b are equivalent to the vertical HPFs 156a, 156b in frequency response, and output a signal expressed by a formula below by each line u2'(m) (m=1, . . . , 256) of the video signal outputted from the vertical 1:2 interpolating circuits 160b, 160d; ##EQU9##
A calculating unit 163a subtracts the output of the vertical HPF 162a from the output of the vertical LPF 161a, while a calculating unit 163b subtracts the output of the vertical HPF 162b from the output of the vertical LPF 161b. Each output from the calculating units 163a, 163b is interpolated with 0 at horizontal 1:2 interpolating circuits a, 164b, and accordingly the number of picture elements in the horizontal direction is increased twice. The output of the horizontal 1:2 interpolating circuit 164a is inputted to a horizontal LPF 165 which is a filter having the same frequency response as the horizontal LPF 152. A signal represented by a formula (3) below is outputted by each line y1'(n) (n=1, . . . , 256) of the video signal outputted from the horizontal 1:2 interpolating circuit 164a; ##EQU10##
In the meantime, an output from a horizontal 1:2 interpolating circuit 164b is inputted to a horizontal HPF 166. The horizontal HPF 166 is a filter with the same frequency response as the horizontal HPF 153, and outputs a signal expressed by a formula (4) below by each line y2'(n) (n=1, . . . , 256) of the video signal outputted from the horizontal 1:2 interpolating circuit 164b; ##EQU11##
A calculating unit 167 subtracts the output of the horizontal LPF 166 from the output of the horizontal LPF 165, and outputs a subtracted signal from an output terminal 168.
Although the conventional sub-band dividing/synthesizing circuit is constructed in the manner as described hereinabove, filtering at the end of the image remains to be solved. In the disclosure "Sub-Band Coding of Monochrome and Color Images" mentioned earlier, although the horizontal and the vertical filters used are filters with 16 taps as indicated in Table 1, values x(-6),...,x(0) and x(257), . . . , x(264) are necessary to perform an operation on each line x (n) (n=1, . . . , 256) of the video signal according to the formula (1) when the video signal is passed through the horizontal LPF 152.
TABLE 1 ______________________________________ LPF HPF ______________________________________ h1(7) 0.48102840 E 00 h2(7) -0.48102840 E 00 h1(6) 0.97798170 E-01 h2(6) 0.97798170 E-01 h1(5) -0.90392230 E-01 h2(5) 0.90392230 E-01 h1(4) -0.96663760 E-02 h2(4) -0.96663760 E-02 h1(3) 0.27641400 E-01 h2(3) -0.27641400 E-01 h1(2) -0.25897560 E-02 h2(2) -0.25897560 E-02 h1(1) -0.50545260 E-02 h2(1) 0.50545260 E-02 h1(0) 0.10501670 E-02 h2(0) 0.10501670 E-02 ______________________________________
Conventionally, as a countermeasure to the above-mentioned problem, it has been practiced that the input signal x(n) (n=1, . . . , 256) to the filter is folded to be connected and operated. In other words, the operation is performed in accordance with a formula (5); ##STR1##
When the video signal is folded for filtering, however, there is a defect such that the resultant subdivided/synthesized image cannot be perfectly returned to the original at an end point thereof. It will be discussed to explain the above defect more concretely when the first line of the inputted video signal x(n) (n=1, ... , 256) is EQU x(1)=16, x(2)=120, x(3)=130, x(4)=140, x(5)=150, x(6)=160, x(7)=170, x(8)=180, x(9)=190, x(10)=200, x(n)=200, (n=11, . . . , 256)
When the first line is passed through the horizontal LPF 152 with 16 taps as shown in Table 1 and thinned out at the horizontal 2:1 sub-sampling circuit 154a, the line is outputted, by the formulae (1) and (5), as; EQU y1(1)=59.6, y1(3)=144.7, y1(5)=152.6, y1(7)=175.1, y1(9)=195.3, y1(11)=200.5, y1(13)=199.8, y1(15)=200.0, y1(17)=199.9,
On the other hand, when the first line is passed through the horizontal HPF 153 and thinned out at the horizontal 2:1 sub-sampling circuit 154b, the line is outputted by the formulae (2) and (5), as; EQU y2(1)=-37.7, y2(3)=8.2, y2(5)=-3.1, y2(7)=1.0, y2(9)=-1.6, y2(11)=0.1, y2(13)=-0.1, y2(15)=0.1, y2(17)=0.0,
If no distortion is generated at all by the sub-band dividing in the vertical direction at the vertical 2:1 sub-sampling circuits 157a-157d of the succeeding stage and by the sub-band-synthesizing in the vertical direction at the vertical 1:2 interpolating circuits 160a-160d, the output of the operating unit 163a becomes y1(n) (n=1,3,5, . . . , 255), and the output of the calculating unit 163b becomes y2(n) (n=1,3,5, . . . , 255). The same folding is performed according to the formula (5) on the output of each operating unit 163a, 163b.
Namely, ##STR2## At this time, the outputs y1'(n) (n=-255,-254, . . . , 511) and y2'(n) (n=-255,-254, . . . , 511) of the horizontal 1:2 interpolating circuits 164a, 164b are ##STR3## Accordingly, the output x1(n) of the horizontal LPF 165 becomes, by the formula (3); EQU x1(1)=46.3, x1(2)=77.9, x1(3)=129.4, x1(4)=156.1, x1(5)=151.0, x1(6)=153.2, x1(7)=169.1, x1(8)=182.0, x1(9)=191.3,
And, the output x2(n) of the horizontal HPF 166 becomes, by the formula (4); EQU x2(1)=45.5, x2(2)=-27.4, x2(3)=-1.8, x2(4)=11.9, x2(5)=0.7, x2(6)=-6.0, x2(7)=-0.7, x2(8)=2.1, x2(9)=1.4,
Therefore, the output X(n) of the calculating unit 167 is, when rounded off to intergers as follows; EQU X(1)=0, X(2)=105, X(3)=131, X(4)=144, X(5)=150, X(6)=159, X(7)=170, X(8)=180, X(9)=190,
Since X(n).noteq.x(n) in the vicinity of the end point of the image (n=1, . . . , 4), the image is impossible to be correctly reproduced.